Retiming Level-Clocked Circuits for Latch Count Minimization
نویسندگان
چکیده
Retiming is a powerful transformation that can minimize the number of memory elements in a sequential circuit under clock period constraints. Recent research has led to the development of extremely fast algorithms for retiming edge-triggered circuits. However, level-clocked circuits have the potential to operate faster and require less memory elements than edgetriggered circuits. This paper addresses the harder problem of retiming level-clocked circuits, and presents a space and time e cient retiming algorithm, called Minaret-L, whose performance compares well with the state of art edge-triggered retiming methods. MinaretL can perform latch count minimization for large circuits (over 56,000 gates) that use multi-phase symmetric clock schedules very e ciently (under 1.5 hours).
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